In microprocessor based systems, there are frequently two data buses that require data transfer to occur asynchronously between them. Frequently, one data bus is byte wide (i.e. eight bits), while the other is word wide (i.e., sixteen bits), or both data buses are word wide. Further, the data on one bus may be from a first block of memory which needs to be transferred to another block of memory connected to the second bus. The data involved in those transfers may start on either byte (i.e., odd) or word (i.e., even) addresses. Further, the length of this data may be of an odd or even byte length. Accordingly, the transfer of a number of data quantities may also end on an odd or even address.
In some communications systems, it is often necessary to transfer large amounts of data between 16-bit processor-based systems. Although the architecture may support sixteen bits, word transfers from odd addresses are still effected by accessing individual 8-bit quantities. In particular, there may be a need for data to be transferred from a word-aligned address to a byte-aligned address, or vice versa. Where only a single byte at a time is transferred, the effective transfer rate of this system is reduced to that of a byte wide system. Therefore, the reduction in the transfer rate may cause a 16-bit processor to deal with 8-bit quantities, thereby diminishing the effect of utilizing the 16-bit processor.
The problems associated with moving byte wide and word wide quantities further extends to even larger buses, such as 32-bit based systems. Again, effective transfer rates are lessened when the system is forced to transfer a single quantity of less than 32-bits in a given transfer cycle.
FIG. 1 illustrates a prior art data transferring system denoted generally at 10. Data transfer system 10 includes a first memory 12 having a first bus 14 and a second bus 16 connected thereto. Data buses 14 and 16 are bidirectionally connected to a DMA controller 18 which includes a temporary register 20 therein. Data transfer system 10 further includes a second memory 22 having a third bus 24 and a fourth bus 26 connected thereto. Third and fourth buses 24 and 26 are also bidirectionally connected to DMA controller 18.
First and second memories 12 and 22 are illustrated as 16-bit memories. For each 8-bit quantity within memories 12 and 22, an individual data bus 14, 16, 24 or 26 is provided to access the corresponding 8-bit quantity. Fir example, first data bus 14 can access even address locations (e.g., X, X+2, X+4, . . . ) within first memory 12. Similarly, second bus 16 may access odd address locations (e.g., X+1, X+3, . . . ) within first memory 12. An external device such as a central processing unit (not shown) may provide information relating to the source in which data is located and the destination to which that data need by transferred. The length, or number of bytes to be transferred, is also typically provided by the external device. Further, an address and a particular memory would be provided for both the source and destination of the data to be transferred. It should be noted that while two independent memories are illustrated, transfer of data may be from one location to another within the same memory. In this instance, data will be transferred along the same bus(es) to and from the single memory.
If a single byte of information is retrieved from an odd address within first memory 12, that information is effectively retrieved as a single byte and written into temporary register 20. Thereafter, the information is written from temporary register 20 to the appropriate destination address within second memory 22. Further, communications are provided between DMA controller 18 and an external device such that the external device may communicate a request for DMA controller 18 to begin operation and post its acknowledgment once it has completed the operation.
A particular inefficiency arises in data transfer system 10 when controller 18 is requested to access information at an odd address and transfer it to an even address. The illustration shown in FIG. 1 depicts first memory 12 having a data quantity "a" located at its first odd address denoted as X+1. Consider the instance where data quantity "a" followed by the additional data quantities "b" through "f" are sought to be transferred to second memory 22 to an even word format. In this instance, data quantity "a" is transferred to even address Y and data quantity "b" is transferred to odd address Y+1. Further, the remaining data quantities "c" through "f" are also to be transferred to word-aligned addresses. In this instance, DMA controller 18 will, in a first transfer cycle, access odd address X+1 via second data bus 16 and store the quantity "a" in the even address D of temporary register 20. Thereafter, the next data quantity "b" stored at address X+2 will be accessed in a second cycle via first data bus 14 and stored at the odd address D+1 of register 20. In a third cycle, the two 8-bit quantities within temporary register 20 will be transferred via third and fourth data buses 24 and 26, respectively, to the first word within second memory 22. From the above, it may be appreciated that three cycles are necessary in order to move the first two 8-bit quantities from a first memory 12 to a second memory 22. Thus, where the first of the two quantities is stored at an odd address and is sought to be transferred to an even address, three cycles are necessary to effect the transfer. Further, in order to transfer the remaining data bytes "c" through "f", an additional six cycles would be necessary such that a total of nine cycles are utilized in order to fully transfer the data string from first memory 12 to second memory 22.
Therefore, a need has arisen for an apparatus and methodology which effectively transfers data between different buses notwithstanding the width of each of the buses. Further, there is a need for an apparatus and methodology which efficiently transfers data from even or odd addresses to even or odd addresses without diminishing the effective system bus bandwidth.